Pseudo Random Bit Sequence Verilog

I suspect there are also examples up on www.altera.com that cover the transceiver toolkit as well. Sorry I don't have any experience with transceivers so I don't know where to point you at. I think the PRBS pattern generation and checking might be implemented in the transceiver block so if you were looking for a code fragment for it you might not find it. If you want to see an example of a PRBS block you can take a look in the /ip directory in any of the zip files on this page: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html Those blocks might be overkill for what you are trying to do but they are programmable and can be setup by a system master like system console over JTAG, Nios II, HPS, etc...