Pseudo Random Bit Sequence Verilog

Thanks for the reply. I prefer to test a physical implementation because I will be reusing the design of this basic implementation for testing an optical device. I've done some research and found that Quartus has megafunctions for instantiating SFP+ ports and the transceiver toolkit that automatically sends PRBS for BER testing. I have been trying to follow this example to get started: http://www.alterawiki.com/wiki/stratix_v_transceiver_phy_basic_design_examples