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Altera_Forum
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9 years ago

Pseudo Random Bit Sequence Verilog

Hi, I want to send a pseudo random bit sequence down a sfp+ port on my Stratix V fpga. Unfortunately I am unfamiliar with verilog. Can anyone help me with this or point me to the right resource...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Typically you would simulate the module. So your simulation would have to drive the CLOCK_50 which if you google around you'll find plenty of examples of how to do that. You would add CLOCK_50, SFP, and maybe the d register to the simulator waveform views so that you can watch it behave over time.