Honored Contributor
Honored ContributorHi Brad,
Thanks for the info. I have below pasted in the 'good path' (setup/hold met). When comparing this path with the one posted yesterday (10/1/08) it can be seen that the timing in the 'good' path is slightly better. Examining the path in the chip plannel i see that the fitter has simply chosen a slightly shorter path for the 'good' fit. Info: Path# 1: Setup slack is 0.241 Info: =================================================================== Info: From Node : SdramFifo:inst3|dff0:inst4|lpm_ff:lpm_ff_component|dffs[0] Info: To Node : N_SLWR Info: Launch Clock : pll_clk_48 Info: Latch Clock : CLK_OUT_48 Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 0.000 0.000 launch edge time Info: 0.110 0.110 R clock network delay Info: 0.387 0.277 uTco SdramFifo:inst3|dff0:inst4|lpm_ff:lpm_ff_component|dffs[0] Info: 0.387 0.000 RR CELL inst3|inst4|lpm_ff_component|dffs[0]|regout Info: 3.415 3.028 RR IC inst3|inst2|dataa Info: 3.960 0.545 RR CELL inst3|inst2|combout Info: 8.637 4.677 RR IC N_SLWR|datain Info: 11.864 3.227 RR CELL N_SLWR Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================================== Info: 20.833 20.833 latch edge time Info: 24.205 3.372 R clock network delay Info: 12.105 -12.100 R oExt N_SLWR Info: Info: Data Arrival Time : 11.864 Info: Data Required Time : 12.105 Info: Slack : 0.241 Info: =================================================================== Info: I'm not sure how to proceed at this point. I know that the timing can be made if the fitter does the right thing. I rather therefore not lower the clock frequency. Are there any other tricks, optimizations etc that can be done to made the fitter 'try harder'? I tried to enable the 'extra' setting in the 'physical synchesis efforts' section in the settings dialog but i now don't meet hold timing in the fast model :(
