Proper method to constrain internal paths in TimeQuest?

Hi Rysc,

This is a Cyclone II, EP2C5Q208C7.

I generated the above report by the following TCL commands (post-fit netlist):

1) create_timing_summary -setup -panel_name "Summary (Setup)"

2) Right clicked on the CLK_OUT_48 clock in the "Summary{Setup)" pane, selected "Report Timing". This results in the following TCL: report_timing -to_clock {CLK_OUT_48} -setup -npaths 10 -detail path_only -panel_name {Setup: CLK_OUT_48}

The location column is available as well as the fanout column when viewed in the "Data Arrival" section of the slack report but these columns for some reason are not visible in the console window.

I'm compiling the QII design in multicorner mode and only the slow model fails. Note that this signal drives an external FIFO that has a 12.1 tsu and 3.6 th requirements. I therefore use the below TCL constraints:

set_output_delay -max -clock [get_clocks CLK_OUT_48] 12.1 [get_ports N_SLWR]

set_output_delay -min -clock [get_clocks CLK_OUT_48] -3.6 [get_ports N_SLWR]

When using the fast model, i see a data arrival time of 5.388 and a data required time of 5.317 (slack 0.071ns). Does this mean that the fitter cannot meet both the tsu in the slow model because it only has 0.071 ns of th to spare in the fast model?

The funny thing is that the timing was met ok until i started constraining other I/O in the design. The fitter for some reason could no longer find a fit that meets timing when more I/Os are involved.

I have attached the external FIFO's timing requirements (Cypress FX2 slave FIFO link). As can be seen the SLWR signal tsu requirement is 12.1ns on a 20.82 ns period clock.

I'm not sure how to fix this so any tips are very much appreciated.

Thanks,

/John.