Dear community, On my PCB design, most of the HPS pins are unused - according to the pin connection guidelines, I should either 'Connect unused pins as defined in the Quartus II software' (for DDR3 related pins) or 'If unused, program it in Quartus as an input with a weak pull-up.'. However, I fail to do so with Quartus II. While I'm perfectly able to program FPGA pins, I am stuck with the HPS pins. How do I program HPS pins? Also, when you go to Quartus II software -> assignments -> settings -> devices -> unused pins. Is this for all pins or just the FPGA pins? Many thanks, Adam

That's pretty much how it works. So if you don't map anything to an HPS pin (HPS peripheral or loan I/O from the FPGA) then whatever the default setting used in your Quartus project will take effect for the HPS I/O as well. I recommend taking a look at the pin connection guidelines at the top of the Cyclone/Arria V SoC documentation pages and look up the HPS pins since they have comments on the right side of table on the recommended default state. From my quick look through it looks like you should be using input tristate with weak pullup.

Hi BadOmen, Thanks for your quick reply! Sorry I forgot to mention that I'm using the Cyclone V SX, but it should be the same for the Arria. Yes, I have been consulting the Pin Connection Guidelines (www.altera.com/literature/dp/cyclone-v/pcg-01014.pdf (http://www.altera.com/literature/dp/cyclone-v/pcg-01014.pdf)), and like you said it gives the recommended setting like 'If unused, program it in Quartus as an input with a weak pull-up.' However, from the Cyclone V Handbook I learn that HPS I/Os are configured by the Preloader. But since Quartus has nothing to do with Preloaders, are you sure that the default setting for pins in Quartus also applies to HPS I/Os? Moreover, in the Quartus Pin Planner (Assignments --> Pin Planner), I cannot assign the HPS Pins to anything - only the FPGA Pins. Thanks, Adam

What the preloader does is takes the I/O settings that Quartus generates and configures the I/O setting registers (this is something that happens automatically on the FPGA side of the chip). This is the main purpose of the scan manager, it's to give boot code direct access to the I/O settings so that software can program their settings because configuring the FPGA doesn't affect the HPS I/O. These are the high level steps: 1) HPS boots 2) Preloader writes the HPS I/O settings into scan manager 3) Preloader writes the HPS pin mux settings into the system manager 4) Preloader "unfreezes" the HPS I/O by accessing the scan manager (this is when the I/O change from tri-state and take on the appropriate role in your design) So if you have unused HPS I/O set to input tri-state with weak pullup that setting is written in step 2 and when step 4 completes those unused I/O will remain set to tri-state (and your used HPS I/O will take the form of whatever your design uses). You are correct, you don't make pin location assignments in Quartus for the HPS I/O because that is handled by the preloader and the pin muxing. You can make other assignments to the HPS I/O like drive strength for example but keep in mind that the HPS I/O are limited in functionality compared to the FPGA I/O so not all of the assignments you are used to will be possible with the HPS I/O.

Hi BadOmen! Thanks for your elaborate reply, really helped me a lot! I have a couple of questions left though: When I create a preloader with the bsp-editor (launched via the SoC EDS 14.0 Command Shell), how do I incorporate the information from Quartus about the pins? How do I set the drive strength of an HPS pin? For the FPGA, I can set the IO-Standard via the pin properties panel in the Pin Planner in Quartus. However, it's grayed out for HPS pins. What's the difference between hps pin mux settings and hps I/O settings? Many thanks, Adam

Hi Adam, --- Quote Start --- When I create a preloader with the bsp-editor (launched via the SoC EDS 14.0 Command Shell), how do I incorporate the information from Quartus about the pins? --- Quote End --- in my understanding, this information is in the "hand-off files" which are generated by Quartus in the assembler phase. (Therefore it is important to run Quartus after a change in Qsys that affects the preloader.) Regards, Thomas www.entner-electronics.com - Home of EEBlaster

Programming HPS pins in Quartus II - Unused HPS Pins

14 Replies

Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Sorry I must have got distracted and forgot to answer those. I'm looking at the design example that comes with the SoC EDS and I can see the pin settings for the HPS I/O in the assignment editor. It'll be rather limited but you can set options like the drive strength of the HPS I/O for example.
--- Quote End ---

Sorry I'm being stupid - but I just can't find it - I've searched the altera soc embedded design suite user guide and the cyclone v handbook but I didn't find anything that tells me how to set the drive strength for HPS I/Os...

--- Quote Start ---
There is a notion of pin muxes in the HPS that reside between HPS peripherals and the HPS I/O. So when you make selections of the peripherals in the HPS component and decide which pin set to use, files are generated that the bsp-editor pulls in to determine how your pin muxes should be setup to route the peripherals to their appropriate HPS I/O. The HPS I/O also have settings like input/output/bidirectional, drive strength, etc... which is determined by your peripheral routing selection as well as I/O constraints you set in Quartus. The I/O settings are also handed off to the bsp-editor so that when the bootloader is generated the correct I/O settings can be programmed into the I/O. Both of these are automated so you shouldn't have to worry about anything except selecting what peripherals and locations you want, generate and compile the hardware and then the bootloader generator (bsp-editor) will take it from there.
--- Quote End ---

Thanks BadOmen!
Altera_Forum
Honored Contributor
11 years ago
To set the HPS I/O drive strength you use the assignment editor (In Quartus). It's the same way as you set the drive strength for FPGA I/O.
Altera_Forum
Honored Contributor
11 years ago
I'm having trouble getting my HPS I/O assignments to do anything. I am trying to change I2C1 from a 3.3V LVTTL to a 3.3V LVCMOS. I enter the assignment into quartus assignment editor. Looking at .fit and .pin reports, it appears like my assignment was honored. However after running Quartus full compilation, there are no changes made to the files in the hps_isw_handoff folder. What am I missing here?
Altera_Forum
Honored Contributor
11 years ago
Those settings get buried in an I/O programming file that gets built into the preloader binary. So you shouldn't see source files change as a result of an I/O standard change since that information is in a separate binary file. I was told that binary programming file gets turned into a C array of values while the preloader is generated/build (not sure which but one of those steps does it) but it's literally just a list of values at that point and you won't know which value maps to what. If that file didn't change then it's possible that switching between 3.3V LVTTL to 3.3V LVCMOS has no effect on the programming file and therefore that C array doesn't change either.

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Programming HPS pins in Quartus II - Unused HPS Pins

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