Programmable watchdog in FPGA

I'm not sure what you're doing, but I repeat my earlier recommendation to change the asynchronous load to a synchronous load if a synchronous load would be suitable for your design. Another possibility is to replace your lpm_counter instantiation with a counter inferred from RTL similar to what you did for your counter that does the divide by 305, but an instantiated lpm_counter with a clock enable port should be fine.

If you really need an asynchronous load, maybe you can use an lpm_latch megafunction (or a latch coded in RTL following the recommended coding style for latches) to capture the asynchronous data and feed the latch output to the synchronous load of lpm_counter. The lpm_latch megafunction will have a proper latch implementation in Quartus unlike the combinational feedback loops you are getting with the lpm_counter asynchronous load. (I did report this lpm_counter design deficiency for asynchronous load to Altera.)

If you still have problems with a synchronous load, try configuring the counter with the MegaWizard in case you did something wrong when you instantiated lpm_counter directly without using the MegaWizard.