Programmable watchdog in FPGA

Thanks Brad for your reply.

It doesn't look like the multicycle statment in sdc file has any effects (don't know why)..However, if this clk_en is NOT set as global routing, I ended up glitches in my output (see timeout signal in the attached waveform). If clk_en is set as global routing. I got no problem..plus..If I look at the Fitter--->Control Signals..I don't see this clk_en listed as global signal..

Any comments?

--- Quote Start ---

Yes, the clock enable is better. My other thread says that you can safely use a divided ripple clock by using global routing and having no synchronous cross-domain paths, but a fast PLL clock with a clock enable is still better (for example, the PLL might have less duty cycle distortion than a clock driven by a register). Instead of doing a divide by 305 to create a clock signal, create a clock enable signal that is asserted every 305th period of the fast clock. Note that the clock enable is asserted for just the 305th period--the assertion lasts for one fast-clock period. The registers using the clock enable are clocked by the fast clock. You can use a multicycle setup of 305 and multicycle hold of 305-1=304 for the paths that use the clock enable for both source and destination registers (see http://www.altera.com/support/examples/timequest/exm-tq-clock-enable.html).

The primary reason to use globals is to minimize skew, which usually matters only for clock signals and does not matter for clock enables. Another reason to use globals is for very high fan-out signals to avoid using up lots of nonglobal routing resources; that's why high-fan-out reset signals typically use global routing.

If there are no timing violations for clock enable paths and you do not run out of global resources, then it does not matter whether the clock enable uses global routing. The global buffer has a big delay that can make setup timing worse than it would be with nonglobal routing. If you have setup violations for clock enable paths, then set "Global Signal" to "Off" for the clock enable in the Assignment Editor or turn off automatic global control signals in the "More Fitter Settings" dialog box. Also, synthesis might take your single divide-by-305 clock enable from your RTL and make lots of different smaller clock enable signals that include additional logic from the RTL; if this happens, you'll see multiple clock enables in the "Control Signals" table in the Fitter report. If synthesis creates multiple clock enable signals without a very large fan-out on any individual signal, then there would be no reason to use a global routing resource for any of these just to cut down on the amount of nonglobal routing used.

--- Quote End ---