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Because the latches are in the COUNTDOWN_COUNTER instance of lpm_counter, I wonder if they result from the asynchronous load. Try setting the top-level entity on the "General" page of the "Settings" dialog box to lpm_counter to see whether you get the warnings for the counter compiled by itself.
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If you have a legitimate use for latches (something that has no suitable clock available, latching data off an asynchronous processor bus, etc.), then check the coding style guidelines in the Quartus handbook to find the correct way to code latches for proper recognition by Quartus integrated synthesis.
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I did essentially this with a counter configured the way you configured yours. I got the combinational loops too. I will report this to Altera. If the asynchronous load is going to use latches, it should be done with proper latches.
If you can change to a synchronous load, that would have less risk of timing hazards.
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