Honored Contributor
Honored Contributorclock constrains as following:
create_clock -period 20 -name 50MHz [get_ports {50MHz}] create_generated_clock -name 10MHz -source [get_ports {50MHz}] -divide_by 5 [get_pins {inst|altpll_component|pll|clk[0]}] create_generated_clock -name counter_clock -source [get_pins {inst|altpll_component|pll|clk[0]}] -divide_by 305 [get_registers {WDT:inst1|intclk}] Does the last constrain make intclk a global? Meanwhile, this is only part of the FPGA functionality, so if I make this global clock..What if I have some other clocks for other functionality which is 'more global'? --- Quote Start --- Hi, just a quick glance for now. If your state_proc is supposed to be combinatorial ,you must contain all signals read inside process in sensitivity list to avoid trouble. your intclk must be made global(through assignment editor) kaz --- Quote End ---