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As I understand it that would take a PLL which I would rather avoid if the functionality comes cheaper.
Looking at the IOE structure there is "programmable delay" but I am guessing
by your comments that this is not _dynamically_ programmable and hence that
would be why it would not show up in altiobuf megafunction params.
Data rate is slow enough at 250MHz DDR LVDS such that I only really
need the dynamic behavior initially for convenience so perhaps I just do a bunch
of builds <tick-tock> with the "fixed" "programmable delay" varied and find my happy place.
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Cosmo,
Quartus II will do a good job inserting IODelays. I'm dabbling (not really) with a similar set-up. I'm using Cyclone IV though which is different than Arria II GX where the DDR registers are built into the IO-ring and the compiler can't add extra routing delay. But I recompiled (QII9.1sp2) my code for Arria II GX and ended up with a really small hold violation of 7 ps for the Fast model only. But I have a skew of 500 ps on the input data at a 240 MHz frequency, you may have a smaller skew and meet timing. After compilation in the Fitter Report -> Resource Section -> Delay Chain Summary you can see what the compiler added.