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Altera_Forum
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15 years ago

Programmable input delay on ARRIA II GX

Using Arria II GX, Vista, Quartus 9.1...

Which megafunction should I be instantiating/using to implement

Programmable input delay on ARRIA II GX.

Inputs are LVDS DDR and need to adjust their phase/delay

relative to the input LVDS clk for correct eye sampling.

Thought is might be altiobuf but it does not seem to have the

option available.

Thoughts?

Thanks,

Cos

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Thanks, FvM.

    As I understand it that would take a PLL which I would rather avoid

    if the functionality comes cheaper.

    Looking at the IOE structure there is "programmable delay" but I am guessing

    by your comments that this is not _dynamically_ programmable and hence that

    would be why it would not show up in altiobuf megafunction params.

    Data rate is slow enough at 250MHz DDR LVDS such that I only really

    need the dynamic behavior initially for convenience so perhaps I just do a bunch

    of builds <tick-tock> with the "fixed" "programmable delay" varied and find my happy place.

    Sound good?

    Cos
  • Altera_Forum's avatar
    Altera_Forum
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    Yes. If you are able to specify the input signal timing, TimeQuest is able to set the delay respectively calculate the expectable margin.

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    As I understand it that would take a PLL which I would rather avoid if the functionality comes cheaper.

    Looking at the IOE structure there is "programmable delay" but I am guessing

    by your comments that this is not _dynamically_ programmable and hence that

    would be why it would not show up in altiobuf megafunction params.

    Data rate is slow enough at 250MHz DDR LVDS such that I only really

    need the dynamic behavior initially for convenience so perhaps I just do a bunch

    of builds <tick-tock> with the "fixed" "programmable delay" varied and find my happy place.

    --- Quote End ---

    Cosmo,

    Quartus II will do a good job inserting IODelays. I'm dabbling (not really) with a similar set-up. I'm using Cyclone IV though which is different than Arria II GX where the DDR registers are built into the IO-ring and the compiler can't add extra routing delay. But I recompiled (QII9.1sp2) my code for Arria II GX and ended up with a really small hold violation of 7 ps for the Fast model only. But I have a skew of 500 ps on the input data at a 240 MHz frequency, you may have a smaller skew and meet timing. After compilation in the Fitter Report -> Resource Section -> Delay Chain Summary you can see what the compiler added.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks, josyb, yes, I just noticed that looking at the results using

    "Locate in Resource Property Editor" for the lvds nodes through Assignment Editor.

    Checking the Fitter Report is much easier. :)

    That's pretty handy dandy and explains why things just worked since i had

    already specified my input timing in sdc file.

    Thanks all!

    Cos