Programmable delay line in CycloneIII

thanks FvM for the hardware test.. in these days I'm a little bit busy because I'm studing for this semester exams, so I cannot spend much time for the fpga project.

However I'll try as you suggested the and/or delay line.

Also the cycloneiii_lcell_comb seem good, if quartus II will do what you want!

I wait that anyone enlighten me about timing constrains...

for ronp, as I says in first post, I'm trying to make a programmable width pulser; previous design use two mc100'195 in parallel, one used to compensate the intrinsic delay of the other; but there is 10 ns from the incoming edge to the output edge of pulse. I think that with the FPGA the delay is quite similar.

The jitter matter is more critical because specifications are better than 100ps cycle to cycle jitter.

thanks again for your interest and replies.

Alessandro Ruggeri