Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Program Counter using VHDL for Altera DE2 Board.

Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic. https://www.alteraforum.com/forum/attachment.php?attachmentid=8350 and here is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes.

All the ifs/elsifs/case statements inside a clocked part of a process will map to logic gates, with the final assignment being the actual register.