Program Counter using VHDL for Altera DE2 Board.

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THere are no latches in an FPGA, only LUTs and registers. A synchronous register can hold the value for you. Latches are prone to glitching and cannot be analysed for timing, so are heavily discouraged in an FPGA (and you will get warnings when they are created in the synthesisor.

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ok thanks Tricky, so you're saying that I should put the if inc=1 condition under the event clock condition, correct?