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Altera_Forum
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12 years ago

Program Counter using VHDL for Altera DE2 Board.

Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic. https://www.alteraforum.com/forum/attachment.php?attachmentid=8350 and here is...
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Altera_Forum
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12 years ago

THere are no latches in an FPGA, only LUTs and registers. A synchronous register can hold the value for you. Latches are prone to glitching and cannot be analysed for timing, so are heavily discouraged in an FPGA (and you will get warnings when they are created in the synthesisor.