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Googling 'VHDL sensitivity list' and reading I see comments like this:
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Also, the synthesis tools (talking about the Xilinx XST in this case)
don't necessarily always respect the process sensitivity list. If you fail to list all the processes whose values are evaluated in the body of the process, the XST will emit a warning saying that it's going to assume that the signals whose values are evaluated are on the sensitivity list. That may lead to differences between behavioral simulations and actual hardware. Keep it in mind.
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Hmmm, guess what I'm experiencing!
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It's even worse with Altera Quartus II: It will output this message:
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Warning (10492): VHDL Process Statement warning at filename.vhd(123): signal "my_signal" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
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From this warning perspective I read it like: Hey, you forgot something, don't you want to add it?
But what it really want's to tell me is: Hey, I changed your code (and so your hardware behavior)! But I don't tell you, you have to find it out yourself by measuring that your hardware doesn't do what you told the compiler to synthesize.
That's contradictory to what you find in educational books about VHDL, e.g. Free Range VHDL:
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For the behavioral architecture description, any time there is a change in signals in the process sensitivity list, all of the sequential statements in the process are re-evaluated.
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In my opinion: Process Sensitivity lists are useless if the compiler doesn't respect what you write there (= the only signals you want the process to be sensitive to). So don't make effort to fill them out, just use the "all" and the compiler will find out itself which signals he thinks the process is sensitive to - and write your process in a way so that it isn't sensitive to signals you don't want the process to be sensitive to, e.g. make sure the signal change you want to respond to really changed.
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