Processes sensitivity list question

Googling 'VHDL sensitivity list' and reading I see comments like this:

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Also, the synthesis tools (talking about the Xilinx XST in this case) don't necessarily always respect the process sensitivity list. If you fail to list all the processes whose values are evaluated in the body of the process, the XST will emit a warning saying that it's going to assume that the signals whose values are evaluated are on the sensitivity list. That may lead to differences between behavioral simulations and actual hardware. Keep it in mind.

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Hmmm, guess what I'm experiencing!

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...also, be warned, the sensitivity list has no influence over the behaviour of your design once it is synthesized. It is only used during simulation. Hence it's quite easy to introduce a difference in behaviour between RTL and synthesized code by changes to the sensitivity list. (Note: Depending on the synthesis tool, the sensitivity list may be ignored, or a latch may be inferred

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Yep! Been there, seen that.

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All of this can be confusing in the case of using VHDL for synthesis because only a subset of the circuits you describe in VHDL can actually be implemented within a FPGA. For example, you can't have a primitive memory element that is sensitive to two independent clock edges, even though you could describe such a circuit by including two clocks in a sensitivity list.

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Guess you really, REALLY have to understand the fundamentals!

Andy