procedure call problem

Ok instead of cutting down here is a full simulation file that I am using in modelsim with comments etc. Attached is a image of the wave I am getting. At the cursor you can see that the rdreq signal gets set when the empty signal goes low. It stays set.

--***************************************************************************************
-- File : test_procedure.vhd
--***************************************************************************************
-- This component is to test the procedure vhdl functionality
--***************************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY test_procedure IS
END ENTITY;
ARCHITECTURE test OF test_procedure IS
--*********************************************************************
--	scfifo component
--*********************************************************************
	COMPONENT scfifo IS
		GENERIC 
		(
			lpm_width				:	natural;
			lpm_widthu			:	natural;
			lpm_numwords			:	natural;
			lpm_showahead			:	string := "OFF";
			lpm_type				:	string := "scfifo";
			lpm_hint				:	string := "USE_EAB=ON";
			intended_device_family	:	string := "Stratix";    
			underflow_checking		:	string := "ON";
			overflow_checking		:	string := "ON";
			allow_rwcycle_when_full	:	string := "OFF";    
			use_eab				:	string := "ON";
			add_ram_output_register	:	string := "OFF";
			almost_full_value		:	natural := 0;
			almost_empty_value		:	natural := 0;
			maximum_depth			:	natural := 0 
		);
		PORT 
		(
			data			: IN std_logic_vector(lpm_width-1 DOWNTO 0);
			clock			: IN std_logic;
			wrreq		: IN std_logic;
			rdreq			: IN std_logic;
			aclr			: IN std_logic := '0';
			sclr			: IN std_logic := '0';
			q			: OUT std_logic_vector(lpm_width-1 DOWNTO 0);
			usedw		: OUT std_logic_vector(lpm_widthu-1 DOWNTO 0);
			full			: OUT std_logic;
			empty		: OUT std_logic;
			almost_full 	: OUT std_logic;
			almost_empty	: OUT std_logic
		);
	END COMPONENT;
	
--*********************************************************************
--	create procedure to read data out of fifo when not empty
--*********************************************************************
	PROCEDURE procedure_example(	SIGNAL clk_i	: IN std_logic;
							SIGNAL reset_i	: IN std_logic;
							SIGNAL empty	: IN std_logic;
							SIGNAL rdreq	: OUT std_logic) IS
		TYPE state_machine IS
		(
			check_empty,
			clear_rdreq
		);
		VARIABLE state : state_machine;
	BEGIN
		IF(reset_i = '1') THEN
			state := check_empty;
			rdreq <= '0';
		ELSIF(clk_i = '1' AND clk_i'EVENT) THEN
			CASE state IS
				WHEN check_empty =>
					IF(empty = '0') THEN
						rdreq <= '1';
						state := clear_rdreq;
					END IF;
				WHEN clear_rdreq =>
					rdreq <= '0';
					state := check_empty;
			END CASE;
		END IF;
	END PROCEDURE;
	
--*********************************************************************
--	create signals for test
--*********************************************************************
	SIGNAL clk			: std_logic;
	SIGNAL reset		: std_logic;
	
	SIGNAL data		: std_logic_vector(15 DOWNTO 0);
	SIGNAL wrreq		: std_logic;
	SIGNAL almost_full	: std_logic;
	
	SIGNAL q			: std_logic_vector(15 DOWNTO 0);
	SIGNAL rdreq_signal	: std_logic;
	SIGNAL empty_signal	: std_logic;
BEGIN
--*********************************************************************
--	example fifo instance
--*********************************************************************
	example_fifo : scfifo
		GENERIC MAP
		(
			lpm_width 		=> 16,
			lpm_widthu 	=> 3,
			lpm_numwords	=> 8,
			almost_full_value => 4
		)
		PORT MAP
		(
			clock			=> clk,
			aclr			=> reset,
			
			data 			=> data,
			wrreq 		=> wrreq,
			almost_full => almost_full,
			
			q			=> q,
			rdreq 		=> rdreq_signal,
			empty 		=> empty_signal
		);
	
--*********************************************************************
--	create clk
--*********************************************************************
	test_clk : PROCESS
	BEGIN
		clk <= '0', '1' AFTER 10 ns ;
		WAIT FOR 20 ns ;
	END PROCESS;
	
--*********************************************************************
--	drive reset
--*********************************************************************
	test_reset : PROCESS
	BEGIN
		reset <= '1';
		WAIT FOR 100 ns;
		reset <= '0';
		WAIT FOR 100 us;
	END PROCESS;
	
--*********************************************************************
--	call procedure concurrently
--*********************************************************************
	test_procedure : procedure_example
		(
			clk_i		=> clk, 
			reset_i	=> reset, 
			empty	=> empty_signal, 
			rdreq		=> rdreq_signal
		);
	
--*********************************************************************
--	fill fifo with dummy data to test procedure 
--*********************************************************************
	test_fill_test_fifo : PROCESS(clk,reset)
		TYPE state_machine IS
		(
			check_full,
			clear_wrreq
		);
		VARIABLE state : state_machine;
		VARIABLE count	: integer := 0;
	BEGIN
		IF(reset = '1') THEN
			state := check_full;
			count := 0;
			data <= (others => '0');
			wrreq <= '0';
		ELSIF(clk = '1' AND clk'EVENT) THEN
			CASE state IS
				WHEN check_full =>
					IF(almost_full = '0') THEN
						data <= std_logic_vector(to_unsigned(count,16));
						wrreq <= '1';
						state := clear_wrreq;
					END IF;
				WHEN clear_wrreq =>
					wrreq <= '0';
					count := count + 1;
					state := check_full;
			END CASE;
		END IF;
	END PROCESS;
END ARCHITECTURE;