procedure call problem

Hi,

Yes I do, I cut down the code a bit too much. I drive the clock and the reset and the empty and rdreq signals are connected to the read side of a scfifo

        test_clk : PROCESS
	BEGIN
		clk <= '0','1' ADTER 10ns;
		WAIT FOR 20 ns;
	END PROCESS;
	
	test_reset : PROCESS
	BEGIN
		reset <= '1';
		WAIT FOR 100 ns;
		reset <= '0';
		WAIT FOR 100 us;
	END PROCESS;
	
	example_fifo : SCFIFO
		GENERIC MAP
		(
			width  => 16,
                        numwords => 8,
                        widthu => 3
		)
		PORT MAP
		(
			clk	=> clk,
			reset	=> reset,
			
			data	=> data,
			wrreq	=> wrreq,
			full	=> full,
			
			q		=> q,
			rdreq	=> rdreq_signal,
			empty	=> empty_signal
		);

The fifo is being filled with data from another component which I have simulated and is working correctly. Data is coming out of the fifo in the simulation as the rdreq is held high but this is not the desired functionality.

Thanks

James