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Altera_Forum
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Honored ContributorProblems working thru "Using Triple-Speed Ethernet on DE2-115 Boards"
I'm trying to get this running.. it is an 'altera corporation - university program' pdf of a triple speed ethernet design. Sort of a bare-bones way to get ethernet working at 10/100/1000 with a NIOS2.
Here are the problems I'm having implementing this with QuartusII-13sp1 web. 1. The megawizard plugin manager keeps crashing and won't generate the my_ddio module 2. The PLL is greyed out for cyclone IV's... not greyed out for cyclone V's. 3. The new TSE modue has some signals I don't know how to connect: tse_mac.pcs_mac_rx_clock and tse_mac.pcs_mac_tx_clock I'm going to guess that I should export those 2 clocks so that they can be 2.5/25/125 MHz depending on enet speed... I have managed to get a my_ddio module from a windows PC running quartus 13sp1 for the my_ddio module, but the altera pll is still greyed out... can I just put the pll in qsys with my processor and export the signals that way? Is there an update to this particular tutorial somewhere? (or a similar example for 13sp1 with a DE2-115 board?) Thanks.30 Replies
Altera_Forumim still having problems with this tutorial..
- Altera_Forum
any luck doing this tutorial with success?
- Altera_Forum
The tutorial is not working for me either. When I run the program, it stuck on soft resetting the second PHY.
Has anybody the same problem and solved it?// Software reset the second PHY chip and wait *(tse + 0xA0) = *(tse + 0xA0) | 0x8000; - Altera_Forum--- Quote Start --- The tutorial is not working for me either. When I run the program, it stuck on soft resetting the second PHY.
Has anybody the same problem and solved it? --- Quote End --- I got it working using Quartus 12 instead of Quartus 13.1 using this tutorial (ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf) and this sources (ftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/de2-115/using_triple_speed_ethernet.zip). But you have to change the pin names like:// Software reset the second PHY chip and wait *(tse + 0xA0) = *(tse + 0xA0) | 0x8000;nios_system system_inst ( .clk_clk (sys_clk), // clk.clk .reset_reset_n (core_reset_n), // reset.reset_n .tse_mac_conduit_connection_tx_clk (tx_clk), // eth_tse_0_pcs_mac_tx_clock_connection.clk .tse_mac_conduit_connection_rx_clk (ENET1_RX_CLK), // eth_tse_0_pcs_mac_rx_clock_connection.clk .tse_mac_conduit_connection_mdc (mdc), // tse_mac_mdio_connection.mdc .tse_mac_conduit_connection_mdio_in (mdio_in), // .mdio_in .tse_mac_conduit_connection_mdio_out (mdio_out), // .mdio_out .tse_mac_conduit_connection_mdio_oen (mdio_oen), // .mdio_oen .tse_mac_conduit_connection_rgmii_in (ENET1_RX_DATA), // tse_mac_rgmii_connection.rgmii_in .tse_mac_conduit_connection_rgmii_out (ENET1_TX_DATA), // .rgmii_out .tse_mac_conduit_connection_rx_control (ENET1_RX_DV), // .rx_control .tse_mac_conduit_connection_tx_control (ENET1_TX_EN), // .tx_control .tse_mac_conduit_connection_eth_mode (eth_mode), // .eth_mode .tse_mac_conduit_connection_ena_10 (ena_10) // .ena_10 ); - Altera_Forum
I tried it and it is worked on Quartus 12 but there is something the .sof file which is generated has the following name (tse_tutorial_time_limited.sof)
did you know if this will make a problem after sometime may be damaged? - Altera_Forum--- Quote Start --- I tried it and it is worked on Quartus 12 but there is something the .sof file which is generated has the following name (tse_tutorial_time_limited.sof) did you know if this will make a problem after sometime may be damaged? --- Quote End --- It is time limited because you don´t have a payed license for the nios-core. The design will only work as long as you have your jtag connected to the board.
- Altera_Forum--- Quote Start --- It is time limited because you don´t have a payed license for the nios-core. The design will only work as long as you have your jtag connected to the board. --- Quote End --- It is worked fine with me Did you have any idea how to send and receive data from computer instead of NiosII?
- Altera_Forum
This is a bit of an old/stale thread. It does rank high on google's search though, so I'm updating it one last time!
I don't know when it happened, but Altera has posted versions of this tutorial for the different versions of the tools. Browse their FTP site: ftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/de2-115/ If you change the "14.0" to your particular version of the tools, you'll find an updated tutorial and the tutorial files. (The forum automatically shortened the link, but you can 'copy link location' or similar to paste it into your browser window or ftp client) - Altera_Forum
Hi Every one I will be lucky If any one still following the post and reply to my question
Did any one try to sniff the packets between eth0 and eth1 by connecting a hub between them , cause when I tried doing so , I didn't receive any frames from the terminal , i had to connect eth0 with eth1 directly with no intermediate devices, can any one advice me why it doesn't work when i connect a hub , thanks and appreciate your help - Altera_Forum
Yes, I used a Netgear GS108E 8port switch. Others should work as well. I connected the two ports of the board to ports 7&8 of the switch with a laptop connected to port 1. I set Wireshark to capture everything and it worked first try. You are on your own getting the OS/Ethernet configured on the laptop side.
Since the example 'sends' to the broadcast, a properly configured switch (and board) will send TWO identical frames, one from each port (look at the Verilog and the TSE example documentation to see why this happens and how to stop it if you desire) to a machine that is listening on any port of the switch. A hub, if you can find one, would work regarless of what MAC you sent to. The GS108E has a port monitor feature, but you don't need it. (I just used the default GS108E factory settings)
