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Honored ContributorProblems working thru "Using Triple-Speed Ethernet on DE2-115 Boards"
I'm trying to get this running.. it is an 'altera corporation - university program' pdf of a triple speed ethernet design. Sort of a bare-bones way to get ethernet working at 10/100/1000 with a NIOS2.
Here are the problems I'm having implementing this with QuartusII-13sp1 web. 1. The megawizard plugin manager keeps crashing and won't generate the my_ddio module 2. The PLL is greyed out for cyclone IV's... not greyed out for cyclone V's. 3. The new TSE modue has some signals I don't know how to connect: tse_mac.pcs_mac_rx_clock and tse_mac.pcs_mac_tx_clock I'm going to guess that I should export those 2 clocks so that they can be 2.5/25/125 MHz depending on enet speed... I have managed to get a my_ddio module from a windows PC running quartus 13sp1 for the my_ddio module, but the altera pll is still greyed out... can I just put the pll in qsys with my processor and export the signals that way? Is there an update to this particular tutorial somewhere? (or a similar example for 13sp1 with a DE2-115 board?) Thanks.30 Replies
Altera_ForumThis was my 2nd FPGA project this summer. I ran into difficulties following the tutorial because it uses verilog(I've been learning VHDL) and it was written for an earlier version of Quartus II (I am using sp13.1) so, the top level instantiation of the NIOSII system does not have the same ports as the top level verilog file(tse_tutorial.v) that is provided with the design files that are on Altera's website:
http://www.altera.com/education/univ/materials/embedded_systems/tutorials/unv-tutorials.html My top level file is in VHDL and works with the other tutorial files. If I can be of help to anyone, please let me know! Omar Fernandes Electrical Engineering '16 The Pennsylvania State University- Altera_Forum--- Quote Start --- anyone manage to solve the problem? --- Quote End --- Yes. I had some faulty cables. The demo worked fine on 12 and 13.
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i've tried doing the tutorial using quartus 12.0...i came across the problem with the pll...how did u solve the pll problem?
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i came up with this problem while compiling in quartus 12.0...it stated
' Node instance "pll_inst" instantiates undefined entity "my_pll" '. - Altera_Forum
i got a new problem with the tutorial...it doesnt have the send> in the terminal of the monitor program....
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any ideas on solving the problem of ethernet 0 and ethernet 1?
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hi I got about 250 errors during compilation saying either:
1. can't generate netlist output files because the file "............" is an OpenCore Plus time-limited file 2. ''can't generate netlist output files because the license for encrypted file "..." is not available" .........does this mean that the "Using Triple-Speed Ethernet on DE2-115 Boards" tutorial is not doable without paying for something or something else? - Altera_Forum--- Quote Start --- hi I got about 250 errors during compilation saying either: 1. can't generate netlist output files because the file "............" is an OpenCore Plus time-limited file 2. ''can't generate netlist output files because the license for encrypted file "..." is not available" .........does this mean that the "Using Triple-Speed Ethernet on DE2-115 Boards" tutorial is not doable without paying for something or something else? --- Quote End --- You need to examine your install settings, you may have installed Quartus incorrectly. And it works just fine with only the tools available/shipped with the board. It also works fine with the web (free) edition of the software. You need to be familiar with Quartus, Qsys (and SOPC builder), how the top level etity ties it all together.... and then you also need to be familiar with eclipse and the EDK-modifications to it -- the BSP and how to download code and later how to generate your hex file for memory initialization so it will run without being tethered. The learning curve is quite steep for FPGA w/soft core processors... Keep at it, but start with simpler examples to make sure your tools are installed correctly.
- Altera_Forum--- Quote Start --- You need to examine your install settings, you may have installed Quartus incorrectly. And it works just fine with only the tools available/shipped with the board. It also works fine with the web (free) edition of the software. You need to be familiar with Quartus, Qsys (and SOPC builder), how the top level etity ties it all together.... and then you also need to be familiar with eclipse and the EDK-modifications to it -- the BSP and how to download code and later how to generate your hex file for memory initialization so it will run without being tethered. The learning curve is quite steep for FPGA w/soft core processors... Keep at it, but start with simpler examples to make sure your tools are installed correctly. --- Quote End --- Ok I'm going back to basics with the My First Nios II tutorial (which I had originally skipped). Can you suggest some other examples or other sources through which I might start learning soft core processors? Many thanks, Rajas
- Altera_Forum--- Quote Start --- Ok I'm going back to basics with the My First Nios II tutorial (which I had originally skipped). Can you suggest some other examples or other sources through which I might start learning soft core processors? Many thanks, Rajas --- Quote End --- Getting a little off topic, but... Work thru that myfirstniosII, and any other examples you would like, exactly as the provided instructions say with the same version of the tools that the example was created with so that any problem you have cannot be blamed on the tools. They are complicated tools, and no one is lucky enough to guess all the configuration options and get a working system. After you get a NIOSII up and running and can single step thru the C code in the debugger in Eclipse... Add a simple FSM to blink an LED at a 0.5hz rate and get that going along with the NIOSII blinking it's own LED and shooting hello world out the jtag-uart (default hello world application in eclipse combined with a simple bit of VHDL (or verilog)) -- I used the myfirstniosII example. Then wire the LED-FSM output and its compliment to the NIOSII as an input and add a 3rd and 4th led controlled (and code to TLE and code to eclipse and connections in QSYS) so that the NIOSII can blink it to 'follow' the FSM's output/compliment. Then make it all fit inside the FPGA, you'll need to figure out how to modify the BSP so that your code will fit... and also when/how to bypass Altera's HAL (and what that is!) And you will probably see eclipse show you some error messages about segments not fitting and you will learn how to fix them. Then start deleting components from SOPC (and adding different ones to interface to the other board HW) and seeing how that works so you know how to connect/configure things like GPIOs and additional uarts. And learn to recognize what is what in Qsys/SOPC. Essentially directed play with the environment. The DMA hookups and code are sort of complex for the TSE if you don't understand how the simple stuff works. Also, there are quite a few changes that need to be made to swap over to the latest version of quartus/qsys... none of them are difficult--all very simple, but there are a lot and if you don't have a rudimentary understanding of how Altera's toolchain works, it is very easy to mess up the TSE example project while 'upgrading' it. The upgrade to Qsys and later versions of the tools essentially gives you upgraded hardware, but for most purposes the old version will probably function sufficiently.
