Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Problems with TimeQuest constraints

I start Timequest timing analysis with constraints for a simple project, a NIOS-II processor, a PIO, an SPI and an SSRAM interface. Although I followed the Altera documentation of "Using SOPCBuilder with Quartus II Software" and "Constraining SOPC Builder Designs with TimeQuest", I get a few warning messages as follows.

Info: Design is not fully constrained for setup requirements

Info: Design is not fully constrained for hold requirements

unconstrained path

From To From clocks

inst|the_pll|the_pll|altpll_component|pll|clk[2] sram_clk clkin

Because the path between inst|the_pll|the_pll|altpll_component|pll|clk[2] and sram_clk are specified, I don't know why I get this warning message. I attach my project here.

Help please, many thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi bcao,

    I believe you can set it to false path with the following command unless specifc tCO/min tCO for the output port is required:

    set_false_path -to [get_ports sdram_clk]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks, golgo

    I don't think that I can specify tCO/min tCO in the TimeQuest?

    Yes, I can by set_false_path -to [get_ports sdram_clk] to get rid of the warning message but the path to sram_clk is not a false path.