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Altera_Forum
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16 years ago

Problems with TimeQuest constraints

I start Timequest timing analysis with constraints for a simple project, a NIOS-II processor, a PIO, an SPI and an SSRAM interface. Although I followed the Altera documentation of "Using SOPCBuilder ...
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Altera_Forum
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16 years ago

Hi bcao,

I believe you can set it to false path with the following command unless specifc tCO/min tCO for the output port is required:

set_false_path -to [get_ports sdram_clk]