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Altera_Forum's avatar
Altera_Forum
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14 years ago

problems with segmented buffer in SignalTAPII

Hello,

I am experiencing strange behaviour with segmented buffers in SignalTapII Logic-Analyzer in quartus II 10.1 (Service Pack 1):

For most buffer organisations only the first acquistion behvaes as expected. When rerunning the analysis or just rereading the data the data shown in the data page does not correspond to the trigger conditions as defined in the setup.

After reprogramming the device it works fine again (for the first acquisition). Some buffer segmentations (8 segments with 8 samples each) seem to work more than once.

It looks to me as if the segment addressing is somehow skewed up.

As anybody seen someting similar before?

I am using the Cyclone II FPGA Starter Board.

Thanks

Wolfgang

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It could be a timing problem... Did you constrain your design? Do you get any critical warning about not meeting the timing requirements?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I constrained inputs and outputs I use in the application, but I did not add any contraints concerning SignalTapII or memory access. Should I add something?

    I don't get any timing violation warnings - just the general info about memory usage and the general hint that violating setup or hold timings here might result in corrupted data.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As long as the clock used by Signaltap is properly defined in timequest it should be correctly analysed. So if you don't get any critical warning it means the timing is fine.

    The other explanation I would see is that some bits are skipped or added in the JTAG flow during the transfer. Are you using an external Blaster? Do you even get errors on the JTAG transfers?

    We had this problem once in a very specific case, using a non-Altera blaster, on a system running under Linux. There seemed to be a conflict between Signaltap and the Linux FTDI driver which caused problems during the data transfer.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am using Linux as OS, but with the on-board USB-blaster.

    My design uses a number of in-system sources and probes which are accessed via the same USB-interface, but the problem also occurs when they are 'quiet'.

    I did not see any errors concerning the JTAG communication.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If you can try from a windows PC instead, it may be worth it. You way have a problem similar to the one I had with the Linux FTDI drivers