Problems with FSM's and Counters

This looks like a clocking problem, where the atate and counter both change while the clock is active and then the new counter value then causes another state change, then another, then another, etc.

If you are not using an edge triggered state flip flop, it may be the cause.

I am an old designer trying to get up to speed, but it looks like VHDL is too complex to be very useful for this level of abstraction even if it is the only game in town.

I have a prototype that I will not be able to fully develop, but it is on a web site if anyone would care to try it. It is based on a tool that I wrote for my own use then evolved thru C, C+, and now C++.

http://mysite.verizon.net/vzeosqt4/simplesimin

I am attaching a tutorial example FSM counter with the VHDL commented out with // and the input text for my programs at the end so you can see the difference.

//I am including a new testcase here. I coded a VHDL example for a FSM. Hope its interesting.

// -- cocurrent process#1: state registers

// state_reg: process(clock, reset)

// begin

//if (reset='1') then

// current_state <= S0;

//elsif (clock'event and clock='1') then

// current_state <= next_state;

//end if;

// end process;

// -- cocurrent process#2: combinational logic

// comb_logic: process(current_state, a)

// begin

//-- use case statement to show the

//-- state transistion

//case current_state is

// when S0 => x <= '0';

// if a='0' then

// next_state <= S0;

// elsif a ='1' then

// next_state <= S1;

// end if;

// when S1 => x <= '0';

// if a='0' then

// next_state <= S1;

// elsif a='1' then

// next_state <= S2;

// end if;

// when S2 => x <= '0';

// if a='0' then

// next_state <= S2;

// elsif a='1' then

// next_state <= S3;

// end if;

// when S3 => x <= '1';

// if a='0' then

// next_state <= S3;

// elsif a='1' then

// next_state <= S0;

// end if;

// when others =>

// x <= '0';

// next_state <= S0;

//end case;

// -- cocurrent process#1: state registers

// state_reg: process(clock, reset)

// begin

//if (reset='1') then

// current_state <= S0;

//elsif (clock'event and clock='1') then

// current_state <= next_state;

//end if;

// end process;

// -- cocurrent process#2: combinational logic

// comb_logic: process(current_state, a)

// begin

//-- use case statement to show the

//-- state transistion

//case current_state is

// when S0 => x <= '0';

// if a='0' then

// next_state <= S0;

// elsif a ='1' then

// next_state <= S1;

// end if;

// when S1 => x <= '0';

// if a='0' then

// next_state <= S1;

// elsif a='1' then

// next_state <= S2;

// end if;

// when S2 => x <= '0';

// if a='0' then

// next_state <= S2;

// elsif a='1' then

// next_state <= S3;

// end if;

// when S3 => x <= '1';

// if a='0' then

// next_state <= S3;

// elsif a='1' then

// next_state <= S0;

// end if;

// when others =>

// x <= '0';

// next_state <= S0;

//end case;

clk.0 @ 0.2

clk.1 @ 1.2

S0.0 @0

S1.1 @ 0 //Set each state to a unique value because current_state will be set to the appropriate value

S2.2 @ 0

S3.3 @0

a.1 @ 4.6

a.0 @ 5.6

reset.1 @ 4

reset.0 @ 5

\c1?!clk

\c2?clk

current_state:S0 ? (current_state == S3)&a | reset

current_state:S1 ? (current_state == S0)&a

current_state:S2 ? (current_state == S1)&a

current_state:S3 ? (current_state == S2)&a

I started to add a GUI for input, but ran out of gas. Also the output could be made much prettier with maybe netlist output for final design usage.