--- Quote Start ---
I understand what you mean about the signals being combinational but I don't understand what you mean about the signals being passed 1 clock cycle early and having them get put through a register. They are all outside of the process block and they need to know the states of the system.
--- Quote End ---
Let's say you have the sequence of states X, Y, Z, Z1 with each state lasting only one clock cycle and no possible branches to or from other states for this part of the state sequence.
If you want output RNS to be asserted during state Y, you can use "RNS<='1' WHEN (state = Y)". The combinational logic creating the RNS signal might have glitches, but it will otherwise be asserted during the time that the state code equals Y plus the propagation delay to create the RNS signal from the state code.
To avoid glitches on signal RNS, you can instead use "RNS_combinational<='1' WHEN (state = X)" and:
process (Clk)
begin
if (rising_edge(Clk)) then
RNS <= RNS_combinational;
end if;
end process;
RNS will be the output of a register that is asserted one clock cycle after RNS_combinational. RNS will be asserted while the state code equals Y as originally intended.
When there are state branches, outputs dependent on inputs, states asserted for multiple consecutive clock cycles, etc., the solution is not that simple. But the basic idea still applies that you can assert a state machine output one clock cycle early and pass it through a register to get the timing you originally intended.
--- Quote Start ---
If you register all your outputs adding one clock cycle of delay for everything, then the relative timing between outputs will be unchanged. You will have an extra clock cycle of latency from input to output, but that might be OK. Your application might not require asserting the combinational signals one clock cycle early to preserve the latency you originally intended.
--- Quote End ---
Now let's say you want output RNS to be asserted during state Y and output REW to be asserted during state Z. You could assert RNS_combinational during state X and REW_combinational during state Y so that registered RNS and REW assert during the intended states Y and Z. But if all you really care is that REW assert one clock cycle after RNS, you can leave the RNS_combinational and REW_combinational assertions during the original states Y and Z and let the registered versions assert in clock cycles Z and Z1, one clock cycle later than originally intended. That might be the best solution if things like state branches in the X, Y, Z part of the state machine make it too much trouble to create a way to assert the combinational versions of the signals one clock cycle early.
--- Quote Start ---
Also since I'm using behavioral vhdl I'm not quite sure how I should put them through a register.
--- Quote End ---
If you are synthesizing the VHDL for programmable logic, then it is technically more correct to say that you are using register transfer language (RTL) instead of behavioral VHDL. If you don't write the VHDL in an RTL style that the synthesis tool understands to infer physical device resources like LUTs and registers, you might get poor synthesis results. Use a reference like those mentioned at
http://www.alteraforum.com/forum/showthread.php?t=1025 to see examples of acceptable coding styles for things like state machines and registers. You can also get examples from the VHDL templates in the Quartus text editor, which is where I got the template for the register process above.
Honored Contributor
