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Altera_Forum's avatar
Altera_Forum
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18 years ago

Problems with FSM's and Counters

I'm having some major problems with this VHDL code. It's supposed to simulate an intersection traffic lights but the behavior that the waveform exhibits doesn't make any sense for the simplest cases...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Right now my clock cycles are too small to really even notice the glitching but it makes the waveform look messy to have it there. I understand what you mean about the signals being combinational but I don't understand what you mean about the signals being passed 1 clock cycle early and having them get put through a register. They are all outside of the process block and they need to know the states of the system. Also since I'm using behavioral vhdl I'm not quite sure how I should put them through a register.