Forum Discussion
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- ... the problem is that there are random blips that seem to pop up for no reason. Here's my code and a waveform to show what I'm talkin about. . . .
RNS<='1' WHEN (state = GoEW OR state = GoEWL OR count = 0 OR EmEW ='1' OR EmEWL='1') ELSE '0';
REW<='1' WHEN (state = GoNS OR state = GoNSL OR count = 0 OR EmNS ='1' OR EmNSL='1') ELSE '0'; --- Quote End --- I can't tell for sure because of the timescale in your waveforms, but it appears that RNS and REW have glitches. These are combinational signals. Combinational signals can glitch unless you carefully design them so that only one LUT or macrocell input at a time can change. To avoid glitches, you can assert these signals one clock cycle early and pass them through a register. The output of the register will have the timing you originally intended without the glitches. If you register all your outputs adding one clock cycle of delay for everything, then the relative timing between outputs will be unchanged. You will have an extra clock cycle of latency from input to output, but that might be OK. Your application might not require asserting the combinational signals one clock cycle early to preserve the latency you originally intended.