Problems when I built my simple system

First you should create a reset pulse instead of leaving the reset_n signal always at 1. Put it at 0 at the beginning for a few clock cycles, and then leave it at 1. This will ensure proper initialization of the components.

For the sink, the filter will put ast_sink_ready at 1 when it can receive data. Then place your data sample on the data input, and put ast_sink_valid to 1. When both the ready and valid signals are at 1, the data is fed to the filter.

For the source from the fft, you must place source_ready at 1 to signal that you can receive data, and the fft will put source_valid at 1 when there is data to read.

The SOP and EOP signals must be put at 1 during one sample only, at the beginning and end of packet. This means that you place them at 1 when required, and reset them to 0 as soon as a transfer occured (i.e. valid and ready at 1 at the same time).

I couldn't open your zip file, it seems corrupted.