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Your reset_n signal is 0, this keeps the component in the reset state. This is why it isn't answering.
For the data bus connection, there might in fact be a simpler way. I assume that the signal that you want to inject to the FFT is in fact real, with no imaginary part. Am I right?
In that case in the component definition you could only define sink_real as data, and define sink_imag as an export. Then outside the SOPC system, just input 0 to sink_imag.
I've never used the DSP IPs in Quartus so I don't know what's the recommended way to connect them...
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Hi, Daixiwen,
Thanks to your advice. Now the warning from the SOPC builder has disappeared after I set the imaginary part input as external input.
I have been trying till just now but still nothing from the output side appears except for the ast_sink_ready_from_the_fir_comp signal. I think it indicates that the FIR is working and has the correct output from the FIR side. Am I right?
In the document of FFT, it says that sink_ready and sink_valid must both be asserted in order to obtain a successful data transfer. However, I cannot view whether these two signals are asserted or not since they are not defined as Avalon conduit interface (they are both defined as Avalon ST interface in the component editor). Is there a way to do so for debugging?
Or is there anything wrong with my input signals in the simulation waveform? Especially for the position and duration of the sop and eop signals, are they correctly asserted? Could you please take a look at the simulation (attached) and give some advice? I truly appreciate for your consistent help. Please don't hesitate to inform me if there are any other files you need for further inspection. Thank you
Best regards
Sincerely
grit
Honored Contributor
