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Altera_Forum
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16 years ago

Problems when I built my simple system

Hi, everyone, I have Cyclone II board and Quartus II 9.0sp2. Now I am trying to build a system containing one FIR compiler and one FFT using SOPC Builder. I am trying to build a system c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi, Daixiwen,

I am so glad to hear from you!

I have set the reset_n signal to be always high and I have also set the sink_sop_to_the_my_fft_0 signal to be always high. However, the output signals (source_imag_from_the_my_fft_0 and source_real_from_the_my_fft_0) still have no response. Yet the ast_sink_ready_from_the_fir_comp_0 signal does goes to high at about 57ns.

Now I guess it is really due to the warning appeared in SOPC previously? I am going to re-edit the fft component as you suggested (keep only one data signal type for the Avalon ST interface). I will update you soon. =)

Best regards

Sincerely

grit