Honored Contributor
Honored ContributorHi, Daixiwen,
Thanks to your kind help previously. Now I have successfully initiated and compiled the whole design. Yet I am still trying to solve the warning data” port; hence the whole project is compiled when the warning still exists at this moment. Now the problem came when I tried to simulate the system using the waveform that defined by myself (please refer to attachment). The result is also attached, in which as you can see there is no output at all. During the simulation, there also appeared 17 warning as follows: warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|fft_s1_cur.last_input" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|fft_s1_cur.check_dav" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|fft_s1_cur.write_input" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|fft_s1_cur.wait_for_input" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|fft_s1_cur.idle" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|asj_fft_dft_bfp_fft_90:\gen_dft_2:bfpdft|asj_fft_bfp_o_fft_90:\gen_cont:bfp_detect|sdet.idle" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|my_fft_0:the_my_fft_0|my_fft:my_fft_0|asj_fft_sglstream_fft_90:asj_fft_sglstream_fft_90_inst|auk_dspip_avalon_streaming_sink_fft_90:auk_dsp_atlantic_sink_1|sink_out_state.empty_and_not_ready" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_source_fir_90:source|source_state.end1" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_source_fir_90:source|source_state.st_err" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_source_fir_90:source|source_state.run1" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_source_fir_90:source|source_state.sop" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_source_fir_90:source|source_state.start" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_sink_fir_90:sink|sink_out_state.empty_and_not_ready" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_sink_fir_90:sink|sink_state.end1" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_sink_fir_90:sink|sink_state.st_err" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_sink_fir_90:sink|sink_state.stall" was synthesized away warning: can't display state machine states -- register holding state machine bit "|fir_fft|fir_fft_sopc:my_system|fir_comp_0:the_fir_comp_0|fir_comp:fir_comp_0|fir_comp_ast:fir_comp_ast_inst|auk_dspip_avalon_streaming_sink_fir_90:sink|sink_state.start" was synthesized away I don’t know if this has anything to do with the warming in SOPC builder after having generated the system. Are there any other possible causes to the outcome? If it has something to do with the warning message, could you please kindly have a look at the vhd files generated for the fft (I believe this is the IP core that I need to modify, however I don't know exactly which file to look at )? Is it easier to create a wrapper or modify the IP core? At this moment, both are hard to imagine for me as I have never done them before. If possible, could you please give me some advice on how to modify the IP core or create the wrapper on my own to put together the real and imaginary parts of the sample in one single 36-bit data vector? Meanwhile I am also trying my best to figure out how to solve these problems. Thank you so much for your help! Best regards grit
