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As the warning says, you can have only one data vector. You should put together the real and imaginary parts of the sample in one single 36-bit data vector.
You need to instantiate your SOPC system in your top level file. If you use the graphical tools, SOPC builder generates a bdf file for you and you can integrate the symbol in your design. If you use vhdl you can have a look at the bottom of the fir_fft_sopc.vhd and look for the test bench. You can them copy-paste the code that declares and instantiate your SOPC component.
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Hi, Daixiwen,
I really appreciate your reply.
Yes, I can find the testbench at the bottom of fir_fft_sopc.vhd. I am going to try to instantiate using that later.
However, for the part of " put together the real and imaginary parts of the sample in one single 36-bit data vector", do you mean I need to modify the IP core? or is there any other simple method for this? I am sorry that I have no clue for that.
Also, I just realize that do I need a PLL to generate the fastclk? If so, it is strange that why the system could be successfully generated?
Thanks you so much in advance for your patience and explanation!
Best regards
Sincerely
grit
Honored Contributor
