Problems using Logic Lock

I'd add that if you are using the 7.0 version of the documentation, the LogicLock methodology is documented, as you said. But in 7.1, the handbook chapters were changed to explain things better. Now the documentation talks about using LogicLock regions to direct placement to a specific part of the chip, but not as a "methodology" to save results. It's covered in the chapter Analyzing and Optimizing the Design Floorplan (http://www/literature/hb/qts/qts_qii52006.pdf). The Incremental Compilation feature is what you'll be using to lock down placement and routing of specific parts of your design, so that's the chapter that will include the detailed instructions. Check out the Recommended Design Flows and Application Examples towards the end of the chapter: Quartus II Incremental Compilation for Hierarchical & Team-Based Design, http://www/literature/hb/qts/qts_qii51015.pdf (pg 57 in the 7.1 version of the doc). The examples should give you some idea of the scenarios where incremental flows would help preserve your results and reduce yoru compilation time.