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I've had some decent results using logic lock--but found that it really wasn't that helpful. Just letting the tool do its thing without my direction seemed to work better--especially when I used Design Space Explorer (DSE) to let it run several iterations.
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That sounds like a comment about using LogicLock to improve performance. On most designs, LogicLock does not improve performance. Given everything else about the state of the design (the source files and the other Quartus settings being used), the Fitter usually provides the best results that can be expected. If you investigate timing violations thoroughly enough, you see that a LogicLock constraint would not result in a better placement for the failing paths even if at first it appears that LogicLock should help. For designs where LogicLock does help with performance, you need to know what you're doing to use it effectively. You can easily make results worse with LogicLock.
For a bottom-up design flow regardless of incremental compilation and for LogicLock used in conjunction with incremental compilation, the appropriate use of LogicLock is to floorplan major blocks of hierarchy. A good floorplan is neutral for its effect on performance. Sometimes a LogicLock floorplan helps performance, but that is the exception. Even for its floorplanning use, LogicLock can hurt performance if used incorrectly or if the design is not architected to make the region-to-region paths not be timing critical.
For BobF's application involving performance preservation and compile-time reduction, floorplanning is an appropriate use of LogicLock for either the old design flow (regardless of that design flow's other limitations) or incremental compilation.
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