Problems using Logic Lock

Brian,

It was one of the design requirements to be able to modify and/or change and /or add new logic to the design and not affect the routing or timing of that which is not changed. We do A LOT of design changes in our work. The design, at present, doesn't use any of the DSPs and only a small amount of the memory. It was forseen that these would be used in the future but it is not wanted to affect that which does work. It was the reason we chose an EP2S60 in the 1020, its more than we need now and we can go bigger in the same package.

I am also having some trouble with the design meeting some of the timing. Its as though I can't add enough timing constraints. When I let the compiler run on its own it fails timing big time. I had been using DSE but sometimes I get better results without it. Its become a real mixed bag, most frustrating.

Functionally everything is perfect and I design with provisions for slack in mind but I've appeared to run into a brick wall. I've never had this much trouble with a design in the seventeen years I've been doing this. All of my attempts to get assistance from Altera have come up empty so I'm reaching out elsewhere.