Problems using Logic Lock

You said, "The design didn't seem to fit ID's requirements". Generally the things the Quartus handbook recommends for the incremental compilation design flow also apply to the old bottom-up LogicLock design flow.

Incremental compilation and LogicLock are two separate features that are used together.

Quartus had a bottom-up design flow before incremental compilation was available. For each project that compiled a portion of the design, the LogicLock region containing that portion was back annotated. A .vqm file was generated. The .vqm file was the post-fit state of the netlist with node names that matched up with the names used for the back annotated locations. Assignments were exported. All this was then imported into the project containing the top level of the design. When this project was compiled, the .vqm files had to be processed by Analysis & Synthesis before the netlist reached the Fitter again. By the time the netlist reached the Fitter in the top-level project, the node names did not always match those in the back annotations, making the back annotations not all work. For some designs, this flow worked well enough. For some designs, it didn't work at all. It might be that your problems are from the limitations of this design flow. Now that incremental compilation is available, use of this old design flow is discouraged.

Incremental compilation solves the limitations of the old design flow. The post-fit netlist and locations are preserved together in a way that the lower-level netlist doesn't have to be processed by Analysis & Synthesis when compiling the top-level design. With this improved method, the node names and locations always match up in the Fitter. LogicLock is used with incremental compilation to floorplan the major blocks of hierarchy so that when one block is recompiled, the Fitter has a single area of the device allocated to that block. That is not always necessary, but it makes the Fitter's job easier than forcing the Fitter to work with small open areas scattered across the device.

Feel free to set an incremental compilation design partition (with an associated LogicLock region for floorplanning, if appropriate), on a small block of the design. The Quartus handbook has guidelines, not hard rules, for this kind of thing. If you have a small block of hierarchy for which you want to preserve the performance, go ahead and put it in its own design partition. It would be best if this block followed the other design guidelines like having its inputs and outputs registered so that you are not likely to create critical timing paths when you isolate this block into its own design partition.