Problems synthesizeing infered true dual ported RAM

Hello Everybody,

I'm pretty new to the Altera World and just hit some problems while trying to synthesize an infering true dual ported RAM. I already found some code snips but I didn't find the 100% match for my case. So now I try to combine these code snips to meet my requirements.

This is the code which is able to be synthesized:

  port_a : PROCESS (clk_a)
  BEGIN
    IF (clk_a'EVENT AND clk_a = '1') THEN
      IF (enable_a = '1') THEN
          v_memory(conv_integer(address_a(c_mem_addr_bits+1 DOWNTO 2)))
             := to_bitvector(data_write_a);
          data_read_a <=
            to_stdlogicvector(v_memory(conv_integer(
              address_a(c_mem_addr_bits+1 DOWNTO 2))));
      END IF;
    END IF;
  END PROCESS port_a;
  port_b : PROCESS (clk_a)
  BEGIN
    IF (clk_a'EVENT AND clk_a = '1') THEN
      IF (enable_b = '1') THEN
          v_memory(conv_integer(address_b(c_mem_addr_bits+1 DOWNTO 2)))
             := to_bitvector(data_write_b);
          data_read_b <=
            to_stdlogicvector(v_memory(conv_integer(
              address_b(c_mem_addr_bits+1 DOWNTO 2))));
      END IF;
    END IF;
  END PROCESS port_b;

But if I try to insert a byte enable signal, it doesn't synthesize anymore. The code is as following (added code is marked blue):

  port_a : PROCESS (clk_a)
  BEGIN
    IF (clk_a'EVENT AND clk_a = '1') THEN                   -- This is Line 157
      IF (enable_a = '1') THEN
        IF (write_byte_enable_a(3) = '1') THEN
          -- 31 DOWNTO 24
          v_memory(conv_integer(address_a(c_mem_addr_bits+1 DOWNTO 2)))
            (31 DOWNTO 24) := to_bitvector(data_write_a(31 DOWNTO 24));
          data_read_a(31 DOWNTO 24) <=
            to_stdlogicvector(v_memory(conv_integer(
              address_a(c_mem_addr_bits+1 DOWNTO 2)))(31 DOWNTO 24));
        END IF;
      END IF;
    END IF;
  END PROCESS port_a;
  port_b : PROCESS (clk_a)
  BEGIN
    IF (clk_a'EVENT AND clk_a = '1') THEN                   -- This is Line 202
      IF (enable_b = '1') THEN
        IF (write_byte_enable_b(3) = '1') THEN
          -- 31 DOWNTO 24
          v_memory(conv_integer(address_b(c_mem_addr_bits+1 DOWNTO 2)))
            (31 DOWNTO 24) := to_bitvector(data_write_b(31 DOWNTO 24));
          data_read_b(31 DOWNTO 24) <=
            to_stdlogicvector(v_memory(conv_integer(
              address_b(c_mem_addr_bits+1 DOWNTO 2)))(31 DOWNTO 24));
        END IF;
      END IF;
    END IF;
  END PROCESS port_b;

As you can see, I just use the highest byte on that 31 bit vector to minimize the possibility of "false code". When I try to synthesize this code, I get the following error messeges:

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][31]" at dp_ram.vhd(202)

Error (10029): Constant driver at dp_ram.vhd(157)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][30]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][29]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][28]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][27]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][26]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][25]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[0][24]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][31]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][30]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][29]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][28]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][27]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][26]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][25]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[1][24]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[2][31]" at dp_ram.vhd(202)

Error (10028): Can't resolve multiple constant drivers for net "v_memory[2][30]" at dp_ram.vhd(202)

Error (12153): Can't elaborate top-level user hierarchy

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 3 warnings

Error: Peak virtual memory: 532 megabytes

Error: Processing ended: Thu Apr 24 10:27:45 2014

Error: Elapsed time: 00:00:05

Error: Total CPU time (on all processors): 00:00:05

To locate the refered lines (157 and 202), I commented them in the posted code snips.

I don't know why the synthesis tool can't handle the byte enable. Can anyone help me to find a workaround?

My second problem hit me when I tried to use two different clock domains to use port_a and port_b independently. Is it due to the internal structure not possible to use a second clock domain on the same RAM? Does there exist a workaround too?

I'm using Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 SJ Web Edition.

Thanks in advance!

Best Regards,

solectrix03