Honored Contributor
Honored ContributorTHe loop problem is because it does not follow the template. If you raise a support request with altera they may try and support it in future, but their answer now will be "it doesnt follow the template, therefore we dont support it". I have had this before with memories inside generate loops that did not use a write-enable, and were generated using FFs. The response was "It does not have a write enable, if you add one then it will be infered" ---etc etc.
As for the memory init - Quartus does not support textio for initialising rams. The annoying thing is that it is supported in Verilog, and Xilinx support it for VHDL. I raised this a few years ago, and to my knowledge it is still not supported. You could re-raise the support request, but unless you threaten to take your massive custom to xilinx, they probably wont do anything about it. Edit: I didnt fully read your post before I pressed send (friday lunchtime pub visit etc etc). I guess they started to support textio for init, but I guess its not complete (as usual - just like their poor attempt at 2008 support).
