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Honored Contributor

8 years ago

Problems probably related to signal propagation (timeQuest questions)

Hi, I have a Terasic DE-10lite board (MAX10 based) and I have designed a controller (in verilog) for the SDRAM on the board. Simulating the project with modelsim, the controller behaves exactly as i ...

multiple-attachments.zip64 KB

Altera_Forum

Honored Contributor

8 years ago

Hi Tricky, thanks for the reply. I use an sdc file with some timing specs. I attach the verilog file that i used and the sdc file.

bit.ly/sdram_vga-v (http://bit.ly/sdram_vga-v) (top module)

bit.ly/sdram_controller-v (http://bit.ly/sdram_controller-v)

bit.ly/sdram_vga-sdc (http://bit.ly/sdram_controller-v)

Thanks to all.

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Problems probably related to signal propagation (timeQuest questions)

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