Forum Discussion
Altera_Forum
Honored Contributor
8 years agoproblem with type matching
Hey guys! I'm having a problem with component instantiation. I keep on getting the an error in modelsim that my types dont match up: # ** Failure: (vsim-3807) Types do not match between compon...
Altera_Forum
Honored Contributor
8 years agoentity wvt is
generic( data_width: integer := 8; image_size: integer := 32; addr_width: integer := 262144 ); port( clk :in std_logic; wvt_rst :in std_logic; start_up :in std_logic; fwvt_iwvt :in std_logic; finished_wvt :buffer std_logic; data_a :in std_logic_vector(data_width downto 0); data_b :in std_logic_vector(data_width downto 0); addr_1 :buffer integer range 0 to addr_width; addr_2 :buffer integer range 0 to addr_width; data_1 :out std_logic_vector(data_width downto 0); we_1 :out std_logic; data_2 :out std_logic_vector(data_width downto 0); we_2 :out std_logic; xread_write_flag: out std_logic; --xtemp_mem1: onedmem((image_size/2-1) downto 0); --xtemp_mem2: onedmem((image_size/2-1) downto 0); xcol_write: out integer range 0 to image_size; xrow_write: out integer range 0 to image_size; xcol_read: out integer range 0 to image_size; xrow_read: out integer range 0 to image_size; xstart_up_hold: out std_logic; xrow_col_switch: out std_logic; xstate: out integer range 0 to 4; xtemp1: out ieee.numeric_std.unsigned((data_width + 1) downto 0); xtemp2: out ieee.numeric_std.signed((data_width + 1) downto 0); xtemp3: out ieee.numeric_std.signed((data_width + 1) downto 0) ); end entity;