Problem with SV Interfaces in Quartus

This will be a contrived example to illustrate a point. I'll start from an incredibly simple module design that does nothing but hold output pins in a constant pattern.

module fpga_tester(
    output  logic          test_byte
);
    initial test_byte = 8'b1010_1010;
endmodule

Building that in Quartus works as expected. I get a message that the output pins are being tied high and low following the 10101010 pattern.

Now, let's try doing the same exact thing, but this time using a structure in the middle. Create a structure, initialize it with the same 10101010, and assign its data to the output pins. The behavior should not change.

typedef struct {
    logic      some_byte;
} my_struct;
module fpga_tester(
    output  logic          test_byte
);
    my_struct test_struct;
    initial test_struct.some_byte = 8'b1010_1010;
    
    assign test_byte = test_struct.some_byte;
endmodule

The result: success. This leads to the exact same result as the previous code.

This is where I get confused. Interfaces, as far as I understand them, allow me to pass register data. That works for me in ModelSim. However, let's rewrite the struct version of the code to use an interface.

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    my_interface test_interface();
    initial test_interface.some_byte = 8'b1010_1010;
    
    assign test_byte = test_interface.some_byte;
endmodule

The result: failure in Quartus. All the output pins are grounded. This gives me the impression that I shouldn't use Interfaces with any logic containing registers, because I cannot predict the result in Quartus. If I run this Interface version in ModelSim, it behaves as I would expect and shows the output pattern of 10101010.

I realize there are workarounds for this specific example. I could easily change the "initial" statement to "assign" and get a continuous assignment that works to hold the output pins in the 10101010 pattern. However, I'm trying to use this example to show a larger problem, which is that interfaces in Quartus don't seem to properly support registers. I originally tried using interfaces in a more complicated design and found that Quartus synthesis results did not match simulation despite the build not having any errors. That led to me making simple test cases like this to see what works and what doesn't. I get the impression that interface support in Quartus is unpredictable. Is that something that may change, or should I stick with structs?