Honored Contributor
Honored ContributorOk i set up my system just like you have shown. A picture is attached. I searched the SDRAM datasheet and Quartus compilation report for pertinent time values and performed the phase shift calculation as it is demonstrated in the ALTPLL Megafunction guide. I used the value I calculated as the phase shift for the SDRAM clock and still I am getting the following error when I try to run program code .
Verifying 00800000 ( 0%) Verify failed between address 0x800000 and 0x80D62F Leaving target processor paused Also I still get the following warnings... Warning: Tri-state node(s) do not directly drive top-level pin(s) Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[15]" to the node "first_nios2_system:inst|sdram:the_sdram|za_da ta[15]" into an OR gate (Continues with an entry for each data and address pin for SDRAM Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "SDRAM_cke" is stuck at VCC Fast Input Register sdram za_data[0] ON Compiler or HDL Assignment There is an entry for each data bit on the sdram. When I check the ignored timing assignments I see this entry... Cut Timing Path On * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module No timing path applicable to specified source and destination I have tried everything to get some type of offchip memory to work on my DE2 board and have yet to succeed. Help Please :/
