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Altera_Forum
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15 years ago

Problem with SDRAM and block schematic

I have a system with SDRAM controller core to connect to SDRAM chip on DE2 board. I know I will need to connect a PLL to the SDRAM clock signal, however I cannot figure out how to do this from my blo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi there, if you are using the SDRAM Controller Core, then I think you are missing a pin. I have made you a little sketch, how I would suggest to wire the design. See the attachment.

I would use the PLL external and use the locked output to reset the core, so you can be sure a valid clk-signal is present. I would then use the "regular" clk to drive the cpu and your controller. The "phase shifted" clock goes directly to the SDRAM. So you will have to find the pin of the FPGA which is connected to the clock pin of the sdram on the de2 and output the shifted clk by this to the sdram.

This is just an example for the normal controller, if you are using the DDR controller I think it is different. Then I would suggest to look into the installationpath under ../altera/ip/../nios2eds/examples/vhdl/.. to find an example for a system with ram.

Good luck.