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Altera_Forum's avatar
Altera_Forum
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9 years ago

Problem with resolving signals in vhdl

Hey guys! I'm dealing with an annoying vhdl problem. I've made a couple of blocks that communicate with each other and now I'm writing a testbench for them. One of the modules is a ram module a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I figured it out, I just have to make a mux that handles this stuff.