Problem with resolving signals in vhdl

Then in that case, with multiple sources, you'll have to build an arbiter that only grants access to the ram one module at a time. Only 1 device can have access to the ram on any given clock cycle. Connecting them all to the addr_a port is just impossible, regardless of the type of addr_a (while a resolved type like std_logic_vector would work in simulation, it would not synthesise as FPGAs do not have internal tri-states).