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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem with resolving signals in vhdl

Hey guys! I'm dealing with an annoying vhdl problem. I've made a couple of blocks that communicate with each other and now I'm writing a testbench for them. One of the modules is a ram module a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Is you DUT the ram? or is the DUT something else? If the DUT is not the ram, why not create a ram model that allows some other mechanism to initialise the ram contents, so you can just let the DUT have exclusive interface to the address interface?

Otherwise, what kind of ram is it? if it has integers as the addr interface, It must be a custom one of your own?

There are many solutions to this problem, but it really depends on the architecture.

Post some code/examples and maybe we can help in more detail.