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Altera_Forum's avatar
Altera_Forum
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8 years ago

Problem with resolving signals in vhdl

Hey guys! I'm dealing with an annoying vhdl problem. I've made a couple of blocks that communicate with each other and now I'm writing a testbench for them. One of the modules is a ram module a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

two options:

1) decide the driver logically (applies to synthesis or testbench)

2) decide the driver based on time sequence using wait statements (applies to testbench only)

The target signal should not be driven otherwise by some fixed driver somewhere else by direct assignment or being portmapped

by the way you can use mif file to initialise the ram if that helps.