Problem with parameters when instantiating custom build component

Hi,

I hope it's okay to revive this thread.
I have had the same problem and solved it by adding a dummy interface to the component whose width was controlled by an otherwise unused generic, that had to be changed from intance to instance.

I called the generic channel_id:

add_parameter channel_id integer
set_parameter_property channel_id DEFAULT_VALUE 1
set_parameter_property channel_id ALLOWED_RANGES 1:64
set_parameter_property channel_id HDL_PARAMETER true
set_parameter_property channel_id AFFECTS_ELABORATION true
set_parameter_property channel_id AFFECTS_GENERATION true

And the interface dummy:

# 
# connection point dummy
# 
add_interface dummy conduit end
set_interface_property dummy associatedClock ""
set_interface_property dummy associatedReset ""
set_interface_property dummy ENABLED false
set_interface_property dummy EXPORT_OF ""
set_interface_property dummy PORT_NAME_MAP ""
set_interface_property dummy CMSIS_SVD_VARIABLES ""
set_interface_property dummy SVD_ADDRESS_GROUP ""

add_interface_port dummy dummy_o dummy Output

As you can see the ENABLED property is set to false, so the interface is not even shown in the platform designer.
In the ellaboration callback I set the width of the output port to the channel_id:

set_port_property dummy_o WIDTH_EXPR "channel_id"

In the VHDL code of the component I added the port, too:

dummy_o : out std_logic_vector(channel_id-1 downto 0);

With these few lines added to the TCL and VHDL files there were individual instantiations created.

I hope this solution works for other users too. I used Quartus Prime 21.1 SE.

Best Regards,
Florian