Problem with multiple entities reading from one input

I can confirm that this kind of hierarchical data pathes works generally well in VHDL.

There are some special requirements if it uses bidirectional inout ports, similar to a real hardware bus, e.g. all connected components must tristate the port and there can be only one driver for a specific data bit unless you are defining resolved signal types.

A simple way to debug design faults is to disconnect and reconnect the components incrementally and watch when the problem appears.